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[Other resource] VHDL.fifo

Description: 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
Platform: | Size: 1178849 | Author: 黎莉 | Hits:

[Other resource] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家
Platform: | Size: 1678507 | Author: SL | Hits:

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[VHDL-FPGA-Verilog] fifo_VHDL

Description: 该文件是先入先出fifo的源代码和测试文件-the document is first-in-first out fifo the source code and test document
Platform: | Size: 7168 | Author: 王立华 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilog] 8_8_FIFO_VHDL

Description: 这是关于VHDL的8*8FIFO源代码，欢迎大家下载使用-This is about 8* 8FIFO The VHDL source code, welcomed everyone to download use
Platform: | Size: 1024 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] ethernet_vhdl

Description: 千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.-Gigabit Ethernet controller. Can adjust FIFO, and the transmission rate, in the code stream control layer.
Platform: | Size: 30720 | Author: 王晶 | Hits:

[Software Engineering] multiplier_8bit

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 46080 | Author: 刘强 | Hits:

[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
Platform: | Size: 4731904 | Author: 李华 | Hits:

[OS Develop] asyn_fifo

Description: verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
Platform: | Size: 2048 | Author: nihao | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
Platform: | Size: 1024 | Author: wd | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo 的vhdl源程序,容量为1024*8的fifo程序代码-fifo the vhdl source code,Capacity of 1024* the fifo code 8
Platform: | Size: 1024 | Author: 谢文华 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: VHDL code for first in first out register
Platform: | Size: 1024 | Author: Davood | Hits:

[VHDL-FPGA-Verilog] fifo1k_32

Description: PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
Platform: | Size: 2048 | Author: dalchan | Hits:

[VHDL-FPGA-Verilog] 8fifo

Description: 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
Platform: | Size: 3072 | Author: qaz | Hits:

[VHDL-FPGA-Verilog] fifi

Description: FIFO code written in VHDL
Platform: | Size: 11264 | Author: Harini | Hits:

[VHDL-FPGA-Verilog] fifo_sync

Description: 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
Platform: | Size: 1024 | Author: zxb | Hits:

[VHDL-FPGA-Verilog] General-memory-VHDL-code-library

Description: 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.
Platform: | Size: 23552 | Author: 周鑫 | Hits:

[Embeded-SCM Develop] fifo

Description: FIFO的VHDL代码，最简单的同步FIFO设计，仅供参考-FIFO VHDL code
Platform: | Size: 403456 | Author: justin | Hits:
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